logic design
e is a fifo design which the clock of data input is running at100mhz,while the clock of data output is running at inputdata is a fix pattern .800 input clocks carry in 800 datacontinuously,and the other 200 clocks carry in no big the fifoshould be in order to avoid data over/under_run?please select theminimum depth below to meet the requirement.
A.160 b.200 c.800 d .1000
osedly there is acombinational circuit between two registersdriven by a will you do if the delay of the combinationalcircuit is greater than the clock signal?
reduce clock frequency increase clock frequency
make it pipelining d to make it multi_cycle
’re working on a specification of a system with some parameter has min,typ and max h columnwould you put setup and hold time?
p time in max,hold time in min
p time in min,hold time in max
in max
in min
e are 3 ants at 3corners of a triangle. They randomly startmoving towards another is the probability that won’tcollide?
a.0
b.1/8
c/1/4
d.1/3
you look at a clock and the time is 3: is angle between the hour and the minute hand?
a.0
b.360/48
3.360/12
d.360/4
many times per day a clock’s hands overlap?
a.11
b.22
c.24
d.26
8.d flip-flop :t_setup=3 ns; t_hold =1 ns; t_ck2q= is the max clock frequency the circuit can handle?
A.200mhz
b.250mhz
c.500mhz
d.1ghz
